This invention pertains to integrated circuit memories, and, more particularly, to charge sharing circuits and methods for an integrated circuit memory.
Numerous charge sharing and charge recycling techniques are known including precharging and sharing charge between bit lines, charge recycling by switching between various power supply levels in charge pumped circuits, and various bus and circuit stacking techniques, as well as combinations of all of these techniques.
Charge sharing techniques have previously been employed in integrated circuit designs in order to save operating power. A typical circuit example is one utilized in conjunction with dynamic random access memory (DRAM) array bitlines which are precharged to a level of VCC/2 then driven to VCC (supply voltage level) or VSS (circuit ground) for the bit line (BL) and complementary bit line bar (/BL or BLB) depending on the state of the previously stored data.
Other contemporary circuit examples include the use of three groups of logic gates operating at three different voltage ranges. In operation, one group will transition from VCC/3 to VSS, the second group from 2 VCC/3 to VCC/3 and the third group from VCC to 2 VCC/3. In this manner, these three groups of logic gates can charge share with their adjacent voltage range group, but conventional designs are constrained to operate in this manner. Stated another way, with current circuit techniques the low level of signal or circuit block A is set equal to the high level of the adjacent signal or circuit block B.
Prior art charge sharing circuits, however, do not have a means for sharing charge or recycling charge in time shifted, clock pipelined circuits. Buses and signals used for charge sharing can be shifted in time by several clock periods in a highly pipelined design. Prior art circuits do not have any means for charge sharing these time shifted electrical signals.
What is desired then, is a circuit and method for efficient charge sharing in an integrated circuit memory during data bus skew applications without undesirably slowing down the data bus or adding a large amount of circuitry.